1. Field of the Invention
The present invention relates to a technique which protects a semiconductor device against electro static destroy (ESD) caused by electro static discharge (ESD) and, more particularly, to a semiconductor device in which a protective element for electro static destroy is formed below a pad.
2. Description of the Related Art
Several techniques for protecting a semiconductor device against electro static discharge (ESD) have been proposed so far. An example is a technique which forms an electro static discharge protecting element (ESD protecting circuit) between a pad and substrate. For example, Jpn. Pat. Appln. KOKAI Publication No. 2003-124336 discloses a device for improving the ESD protection performance of a semiconductor integrated circuit (CMOS). In this device, a passive element (polysilicon resistor) is formed below a bonding pad and above a non-conductive layer formed on a substrate. The device is characterized in that this polysilicon resistor is placed between the bonding pad and an integrated circuit and connected to them.
The main purpose of this device disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2003-124336 is to reduce the stress in the bonding pad. From the viewpoint of ESD protection, it is difficult to say that the ESD protection performance of this device is improved, since the polysilicon resistor is simply inserted between the bonding pad and integrated circuit.